dram configuration
本项目存在于子选单中会显示由bios 自动侦测与dram 相关的信息。
memory clock frequency [auto]
设定内存时脉频率。设定值有：[auto] [ddr2 400] [ddr2 533] [ddr2 667] [ddr2 800]
tcl [auto]
设定值有：[auto] [3] [4] [5] [6]
trcd [auto]
设定值有：[auto] [3] [4] [5] [6]
trp [auto]
设定值有：[auto] [3] [4] [5] [6]
tras [auto]
设定值有：[auto] [5] [6] [7] ~ [18]
1t/2t memory timing [auto]
设定内存的定时器。设定值有：[auto] [1t] [2t]
dram ecc enable [disabled]
开启或关闭dram ecc 功能设定值有：[disabled] [enabled]
进阶内存设定（advance memory settings）
cpu on-die termination
设定值有：[auto] [300ohm] [150ohm] [75ohm]
trc
设定值有：[auto] [11] [12] [13]...[25] [26]
twr
设定值有：[auto] [3] [4] [5] [6]
trrd
设定值有：[auto] [2] [3] [4] [5]
trwt
设定值有：[auto] [2] [3] [4] [5] [6] [7] [8] [9]
twtr
设定值有：[auto] [1] [2] [3]
trtp
设定值有：[auto] [2/4] [3/5]
twrrd
设定值有：[auto] [0] [1] [2] [3]
twrwr
设定值有：[auto] [1] [2] [3]
trdrd
设定值有：[auto] [2] [3] [4] [5]
tref
设定值有：[auto] [undef] [7.8 us] [3.9 us]
trfc
设定值有：[auto] [0] [1] [2] [3] [4]
dram termination
设定值有：[auto] [disabled] [75 ohms] [150 ohms] [50 ohms]
max async latency
设定值有：[auto] [0 ns] [1 ns] [2 ns] [3 ns]...[14 ns] [15 ns]
r/w queue bypass
设定值有：[auto] [2x] [4x] [8x] [16x]
dynamic idle cycle counter
设定值有：[auto] [disabled] [enabled]
idle cycle limit
设定值有：[auto] [0 cycles] [4 cycles] [8 cycles] [16 cycles] [32 cycles] [64 cycles] [128 cycles] [256 cycles]
dcq bypass maximum
设定值有：[auto] [0x] [1x] [2x] [3x]...[14x] [15x]
dram burst length
设定值有：[auto] [64-byte] [32-byte]
rdpadrcvfifo delay
设定值有：[auto] [1.5] [2] [2.5] [3] [3.5]
disable jitter
设定值有：[auto] [off] [on]
dram bank interleaving
configuration options: [disabled] [enabled]
bank swizzle mode
configuration options: [disabled] [enabled]
dram 计时控制（dram timing control）
cke fine delay
设定值有：[auto] [no delay] [1/64 memclk delay] [2/64 memclk delay] [3/64 memclk delay] [4/64 memclk delay] [5/64 memclk delay]...[30/64 memclk delay] [31/64 memclk delay]
cke setup time
设定值有：[auto] [1/2 memclk] [1 memclk]
cs/odt fine delay
设定值有：[auto] [no delay] [1/64 memclk delay] [2/64 memclk delay] [3/64 memclk delay] [4/64 memclk delay] [5/64 memclk delay]...[30/64 memclk delay] [31/64 memclk delay]
cs/odt setup time
设定值有：[auto] [1/2 memclk] [1 memclk]
address/command fine delay
设定值有：[auto] [no delay] [1/64 memclk delay] [2/64 memclk delay] [3/64 memclk delay] [4/64 memclk delay] [5/64 memclk delay]...[30/64 memclk delay] [31/64 memclk delay]
address/command setup time
设定值有：[auto] [1/2 memclk] [1 memclk]
read dqs timing control
设定值有：[auto] [no delay] [1/64 memclk delay] [2/64 memclk delay] [3/64 memclk delay] [4/64 memclk delay] [5/64 memclk delay]...[46/64 memclk delay] [47/64 memclk delay]
write data timing control
设定值有：[auto] [no delay] [1/64 memclk delay] [2/64 memclk delay] [3/64 memclk delay] [4/64 memclk delay] [5/64 memclk delay]...[46/64 memclk delay] [47/64 memclk delay]
dqs receiver enable timing
设定值有：[auto] [0 ps] [50 ps] [100 ps] [150 ps] [200 ps] [250 ps] [300 ps] [350 ps] [400 ps]...[8550 ps] [8600 ps] [8650 ps] [8700 ps]
output driver control
cke drive strength
设定值有：[auto] [1.00x] [1.25x] [1.50x] [2.00x]
cs/odt drive strength
设定值有：[auto] [1.00x] [1.25x] [1.50x] [2.00x]
add/cmd drive strength
设定值有：[auto] [1.00x] [1.25x] [1.50x] [2.00x]
memclk drive strength
设定值有：[auto] [0.75x] [1.00x] [1.25x] [1.50x]
data drive strength
设定值有：[auto] [0.75x] [1.00x] [1.25x] [1.50x]
dqs drive strength
设定值有：[auto] [0.75x] [1.00x] [1.25x] [1.50x]
dram drivers weak mode
设定值有：[auto] [normal] [weak]
amd cool 'n' quiet function [enabled]
开启或关闭amd cool'n'quiet 技术。设定值有：[disabled] [enabled]
amd live! [disabled]
设定值有：[enabled] [disabled]